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A 32-bit VHDL processor with 26 instructions, including jumps, branches, and function calls. Implementing an FSM for execution control and testing using Quartus and ModelSim.

This repository includes Logisim Evolution circuits for a 3-Bit Down Counter, BCD to Excess-3 Converter, BCD to Hex Display, 4-Bit Comparator, and Cache Memory, covering sequential logic, number ...

VYUsync’s HEVC 4Kp60, 4:2:2, 10-bit Decoder Core is a highly optimized universal video decompression engine. The Decoder has been tested with more than 3000 industry standard test streams and is ...

Naturally, as the counter is a standalone device containing mainly just a handful of SN74141 drivers and SN7490 BCD counters, there was no I2C connectivity available out of the box. At the same ...

Instead of going with silicon-based switching (ie: transistors) this 4-bit adder uses mechanical relays. We like it for its mess of wires (don’t miss the “assembly” page which is arguably ...