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A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS | IEEE Journals & Magazine | IEEE Xplore
A PAM-4 clock recovery scheme is proposed that reduces the number of required edge samplers for a PAM-4 bang–bang phase detector without degrading the jitter tolerance of the receiver. Using an AFE as ...